The present invention generally relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device including a vertical transistor and a method of fabricating the same.
In the case of semiconductor devices such as a DRAM, high technology is required to include more transistors in a limited area, thereby increasing a degree of integration. As a result, a vertical transistor has been suggested in which memory cells are located in a small area. In the case of memory devices, the vertical transistor has a surrounding gate structure that surrounds a vertical channel of the transistor.
A channel region is selectively isotropic-etched to form the surrounding gate in 4F2 so that the channel region is thinner than a source/drain region, thereby obtaining an excellent device characteristic. As a result, the vertical transistor can effectively use a limited area. Also, the vertical transistor has been spotlighted as a transistor in various fields as well as DRAM because it is easy to obtain a smaller-sized transistor.
In the manufacture of semiconductor devices, the degree of integration has to be increased to form more devices in a limited area. For improvement of the degree of integration, a vertical transistor is formed. The vertical transistor includes memory cells in a small area. The vertical transistor includes a surrounding gate structure that surrounds a vertical channel structure.
Although the device area is reduced, the vertical transistor maintains an effective channel length, thereby providing an effective structure against Short Channel Effect (SCE). The surrounding gate maximizes controllability of a gate, thereby improving the characteristic for SCE. The surrounding gate also has an excellent operating current characteristic because the current flowing area is the greatest as compared with other gate structures. In order to increase the degree of integration, the vertical transistor is required to have a slender and taller structure.
However, a memory cell having a line width of less than 50 nm has a very thin channel structure, which can collapse. The danger of the collapse associated with such a thin channel structure hinders high-integration of the vertical transistor. The vertical transistor having a regular thickness is structurally stable, but the vertical transistor having irregular thickness degrades a structural stability. The unstable vertical transistor can collapse in a subsequent process and generate particles over a wafer, thereby reducing yield of the device. As a cross-sectional area of the vertical transistor is decreased, the vertical transistor may be broken when uniformity is poor during a locally isotropic etching process.